PowerPC Processor

The original idea for the PowerPC architecture came from IBM’s Power architecture (introduced in the Risc/6000) and retains a high level of compatibility with it. The intention was to build a high-performance, superscalar low-cost processor.

History Of Power-PC:

The history of the PowerPC began with IBM’s 801 prototype chip of John Cocke‘ s(IBM Watson Research Lab) RISC ideas in the late 1970s (with further refinements developed by David Paterson). 801-based cores were used in a number of IBM embedded products, eventually becoming the 16-register ROMP (Research Office Products Division Micro Processor was a 10 MHz RISC microprocessor designed by IBM in early 1980) processor used in the IBM RT(computer workstation by IBM). The RT had disappointing performance and IBM started the project to build the fastest processor on the market. The result was the POWER architecture, introduced with the RISC System/6000 in early 1990.

PowerPC Processor Architecture:

A PowerPC family microprocessor having consisted of a basic block diagram with a branch processor, a fixed-point processor, and a floating-point processor. This microprocessor consists of the sequencing and processing controls for instruction fetch, instruction execution, and the interrupt action, and it implements the instruction set, storage model, and other facilities defined in the POWER PC family architectures. The PowerPC family microprocessor can execute the following classes of instructions:

• Branch instructions.
• Fixed-point instructions.
• Floating-point instructions.

The process begins at the highest with Branch Processing, which branches to either fixed-point or float-point processing. These processes send and receive data from storage. Storage also will send more instructions to Branch Processing at the highest of the diagram. To execute the above block diagram in a chip with any instructions like ARM or any other processor architecture, it has also set of instruction architecture. These registers are in the CPU that is used for 32-bit applications and are available to the user.

The Power PC processing unit may be a word-oriented, fixed-point processor functioning in together with a double-word-oriented, floating-point processor. The microprocessor uses 32-bit word-aligned instructions. It provides for byte, half-word, and word operand fetches and stores for fixed point, and word and double-word operand fetches and stores for floating-point. These fetches and stores can occur between main storage and a group of 32 general-purpose registers, and between main storage and a group of 32 floating-point registers.

In order to maintain RS/6000 software compatibility, the PowerPC adapted the POWER architecture, and many enhancements were added to provide a low-cost, single-chip, super-scalar, multiprocessor capable, and 64-bit processor.

• In order to maintain RS/6000 software compatibility, the PowerPC adapted the POWER architecture, and many enhancements were added to provide a low-cost, single-chip, superscalar, multiprocessor capable, and 64-bit processor.
• Complex string instructions were left out, consistent with the RISC philosophy.
• Instructions whose operation was dependent on the value of source operand were eliminated.
• Precision shifts, integer multiplies, and divide-with-reminder instructions were omitted.
• Support for operation in both big-endian and little-endian modes.
• A single and double-precision floating-point arithmetic 64-bit architecture, backward compatible to 32-bit.

Architecture may be a specification of the functionality that has got to be provided on a microprocessor. Although it is meticulously and legalistically specific about how instructions must behave, the architecture makes no requirements on how that instruction must be implemented in hardware, or maybe that it must be implemented in hardware. In more simply you’ll say, the PowerPC ISA is an agreement between software and therefore the hardware platform that it’s executed. the planning features like pipe-lining, superscalar dispatch, and parallel execution are a part of an implementation’s microarchitecture. Such features are commonly related to RISC architecture, and the PowerPC architecture is defined to form it easy to implement such features, but the architecture does not require them. during a sense, the architecture is that the ordering that guarantees a standard, clearly defined functionality, and allows some traits to be pervasive across the broader family, others to be common to smaller groups within a family, etc all unique to every individual.