UART Protocol Tutorial
We call this the UART protocol. When a frame is not being sent, the signal is high. When a signal is to be sent, a start bit, which is low. is sent for one-bit time. The frame, from five to eight bits long, is then sent one bit per bit time, least-significant bit first. A parity bit may then be sent and may be generated so that the parity of the whole frame is always even (or always odd). To generate even parity, if the frame itself had an even number of ones already, a low parity bit is sent; otherwise, a high bit is sent. Finally, one or more stop bits are sent. A stop bit is high and is indistinguishable from the high signal that is sent when no frame is being transmitted. In other words, if the frame has n stop bits (n – 1, 1 lh. or 2) this means the next frame must wait that long after the last frame bit or parity bit of the previous message has been sent before it can begin sending its start bit. However, it can wait longer than that. The *A4 and ‘B32 ‘ have a UART-like device called the Serial Communication Interfaces (SCIO). The SCIO device shown in Figure 11.13 is often used by the debugger. When not so used, it can be available for serial communication in an experiment or project. We describe its data, baud rate of the generator, and control and status ports. Then we will show how the SCI can be used in the gadfly synchronization interface.
The UART Protocol provides asynchronous communications commonly referred to as RS-232 or RS-485. The UART Protocol component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality differing only in the number of resources utilized.
To assist with the processing of the UART receive and transmit data, the independent size of the configurable buffers is provided. The independent circular receive and transmit buffers in SRAM, as well as hardware FIFOs, help to ensure that data will not be missed while allowing the CPU to spend more time on critical of the real-time tasks rather than servicing the UART.
For most use cases the UART Protocol can be easily configured by choosing the BAUD rate, parity, number of data bits, and number of start bits. The most common configuration for RS-232 is often listed as “8N1” which is shorthand for 8 data bits, No parity and 1 stop bit which is also the default for the UART component. Therefore in most applications, only the BAUD rate must be set. A second common use for UARTs is in multi-drop RS-485 networks. The UART component supports 9-bit addressing mode with the hardware address detect, as well as a TX output enable signal to enable TX transceiver during the transmissions.
The long history of the UART Protocol has resulted in many physical layer and protocol layer variations over time including but not limited to RS-423, DMX512, MIDI, LIN bus, legacy terminal protocols, and IrDa. To support the UART variations commonly used, the component provides configuration of the support for the number of data bits, stop bits, parity, hardware flow control,
As a hardware-compiled option, you can select to output a clock and serial data stream that outputs only the UART data bits on the clock’s rising edge. An independent clock and data output are provided for both the TX and RX. The purpose of these outputs is to allow the automatic calculation of the data CRC by connecting a CRC component to the UART Protocol.
Features Of UART Protocol:
• 9-bit address mode with hardware address detection
• BAUD rates from 110 – 921600 bps or arbitrary up to 3 Mbps
• RX and TX buffers = 1 – 65535
• Detection of Framing, Parity,
• Full Duplex, Half Duplex, TX only and RX only optimized hardware
• 2 out of 3 votings per bit
• Break signal generation and detection
• 8x or 16x oversampling.
When to Use a UART Protocol?
The UART should be used any time that a compatible asynchronous communications interface is required especially RS-232 and RS-485 and other variations. The UART can also be used to create more advanced asynchronous based protocols such as DMX512, LIN,
A UART Protocol should not be used in those of the cases where a specific component has already been created to address the protocol. For
Bits per second
This parameter defines the baud-rate
Data bits
This parameter defines the number of data bits transmitted between the
- 8 data bits are the default of the configuration sending a byte per transfer.
- 9-bit mode does not transmit 9 data bits; the 9th bit takes of the place of the parity bit as an indicator of address using Mark/Space parity. Mark/Space parity of them should be selected if 9 data bits mode used.
Parity Type:
This parameter defines the functionality of the parity bit location of the transfer. This can be set to None (default), Odd, Even, or Mark/Space. If you selected 9 data bits, then select Mark/Space as the Parity Type.
API control enabled:
This checkbox is used to change parity by using the control register and the UART_WriteControlRegister() function. The parity type can be dynamically changed between bytes without disrupting the UART operation if this option selected, but the component will use more resources.
Stop bits:
This parameter defines the number of stop bits implemented in the transmitter. This parameter can be set to the 1 (default) or 2 data bits.
Flow Control:
This parameter allows you to choose between the Hardware or None (default). When this parameter is set to the Hardware, the CTS and RTS signals become available on the symbol.
Hardware Configuration Options:
UART Protocol Clock Selection:
This parameter allows you to then the choice between an internally configured clock or an externally configured clock or
UART Protocol Address Mode:
This parameter defines how hardware and software interact to handle device of the addresses and data bytes. This parameter can be set to the following types:
- Software Byte-by-Byte – Hardware indicates the detection of the address byte for every byte received. The software must read the byte and determine if this address matches the device addresses defined as in Address #1 or Address #2 parameters.
- Software Detect to Buffer – Hardware indicates the detection of an address byte and software will copy all data into the RX buffer defined by the RX Buffer Size parameter.
- Hardware Byte-By-Byte – Hardware detects of a byte and forces an interrupt to move all data from the hardware FIFO into the data buffer defined by RX Buffer Size.
- Hardware Detect to buffer – Hardware detects a byte and forces an interrupt to move the only the data (address byte is not included) from the hardware FIFO into the data buffer defined by RX Buffer Size.
- None – No RX addresses the detection of the implemented.
Hardware TX Enable:
This parameter enables or disables the use of the TX-Enable output of the TX UART. This signal is used in RS-485 communications. The hardware provides the functionality of the output automatically, based on buffer conditions.
Advanced Features:
- Break signal bits – Break signal bits parameter enables the Break signal of the generation and detection and defines the number of logic 0s bits transmitted. This option will save resources when setting to None.
- Enable 2 out of 3 votings per bit – The Enable 2 out of 3 votings per bit enables or disables error compensation algorithm. This option will save resources when disabled. For more information, refer to the Functional Description section of this datasheet.
- Enable CRC outputs – The Enable CRC outputs of the parameter enables or disables tx_data, tx_clk, rx_data, rx_clk outputs. They used to output of the clock and serial data stream that outputs only the UART data bits on the clock’s rising edge. The purpose of these outputs is to allow the automatic calculation of the data CRC. This option will save resources when disabled.
